The present invention relates to a semiconductor device, and more particularly, to a delay circuit of a semiconductor device.
Generally, a semiconductor device, e.g., a double data rate synchronous dynamic random access memory (DDR SDRAM), includes a plurality of delay circuits for various purposes. The delay circuit is configured to delay an input signal by a predetermined time. The delay circuit may be implemented using logic gates, resistors, capacitors, and so on.
FIG. 1 illustrates a schematic circuit diagram of a conventional delay circuit. Referring to FIG. 1, the conventional delay circuit includes an inverter INV configured to receive an input signal IN, a resistor R connected between a node A, i.e., an output node of the inverter INV, and an output node B, and a capacitor C connected between the output node B and a ground terminal VSS.
The inverter INV includes a PMOS transistor PM and an NMOS transistor NM. The PMOS transistor PM has a source connected to an external voltage terminal VDD_EXT, a drain connected to the node A, and a gate receiving the input signal IN. The NMOS transistor NM has a drain connected to the node A, a source connected to the ground terminal VSS, and a gate receiving the Input signal IN.
A delay time of the delay circuit is determined by resistance and capacitance of a path through which the input signal IN is transferred. The resistance of the path means a sum of an on resistance of the inverter INV driving the node A, a parasitic resistance generated due to a line on the path, and a resistance of the resistor R. The capacitance of the path means a sum of a capacitance of the line itself, a parasitic capacitance on the gates of the transistors PM and NM receiving the input signal IN, and a capacitance of the capacitor C for the intended delay.
Eq. 1 below shows the relationship between the delay time, the resistance and the capacitance.Td∝(Ron+RL)×CL  Eq. 1where Td is the delay time, Ron is the on resistance of the inverter INV, RL is a sum of the parasitic resistance of the line and the resistance of the resistor R, and CL is a sum of the capacitance of the line itself, the parasitic capacitance on the gates of the transistors, and the capacitance of the capacitor C.
As can be seen from Eq. 1, the delay time of the delay circuit increases when the resistance or capacitance increases, but decreases when the resistance or capacitance decreases.
An external voltage of the external voltage terminal VDD_EXT is applied to the inverter INV. As the external voltage increases, the on resistance of the inverter INV decreases and thus the delay time decreases. That is, the inverter INV has a propagation delay characteristic that the delay time decreases as the external voltage increases. If the voltage applied to the Inverter INV is not the external voltage but an internal voltage having a predetermined voltage level, the inverter INV has a propagation delay characteristic that it has a constant delay time regardless of the external voltage. Further, since the ground terminal VSS is connected to the capacitor C, the delay circuit has a propagation delay characteristic that it has a constant delay time regardless of the external voltage.
In a data read/write operation, the DDR SDRAM must ensure a sensing margin time, that is, a time until an amplification operation of a bit line sense amplifier is started after a word line is activated. To ensure the sensing margin time, the delay circuit is required to have a propagation delay characteristic that the delay time increases as the external voltage increases. Therefore, an additional delay circuit must be designed according to the external voltage. Further, the sensing margin time cannot be ensured when the delay time decreases as the external voltage increases. In this case, polarity of data may be changed.